1. Field of the Invention
Embodiments of the present invention relate generally to a partial response maximum likelihood (PRML) data detection and clock recovery apparatus and method. More particularly, the present invention relates to a high-speed mixed digital/analog PRML data detection and clock recovery apparatus and method for data storage requiring less area, results in reduced power consumption, and has an improved operation speed.
2. Description of the Related Art
PRML signal processing is a signal processing technique for a computer hard disc, or an optical disc read channel, which have been widely employed in recent years due to their high storage density and transfer rates. The PRML-related technologies have also advanced, with many implementations for the same being proposed.
FIG. 1 is a block diagram of a reproducing and/or recording apparatus, e.g., a general optical disc system. In FIG. 1, the exemplary optical disc system includes a pickup 20 for reading in data recorded in an optical disc 10, such as a digital versatile disk (DVD) or a compact disc (CD), or the like, an RF block 30 for generating an RF signal from a signal read in by the pickup 20, a data processing (DP) block 90 for processing the RF signal output from the RF block 30, and a PRML block 80 for improving and transferring to the DP block 90 a bit error rate (BER) of the RF signal output from the RF block 30. With this arrangement, the reproducing and/or recording apparatus can implement reading from and recording to a medium, e.g., the optical disc system reading from and recording to an optical disc.
FIG. 2 is a block diagram of a conventional PRML block. In FIG. 2, the conventional PRML block includes an analog amplification and equalization part 50, an A/D converter 52, a DC offset remover 54, a clock recovery circuit 70, an adaptive digital equalizer 56, a level error detector 58, and a Viterbi decoder 60.
The analog amplification and equalization part 50 has plural D/A converters 41 and 42, a variable gain amplifier 44, an analog equalizer 46, and an analog gain control (AGC) controller 48.
The variable gain amplifier (VGA) 44 amplifies an input RF signal, and the AGC controller 48 maintains the level of a signal output from the analog equalizer 46 constant. The analog equalizer 46 uses a low-pass filter to equalize the RF signal amplified by the variable gain amplifier 44.
The bandwidth and boosting gain of the low-pass filter are adjusted depending on fixed parameters. A signal equalized and output by the analog equalizer 46 goes through sampling by the A/D converter 52, and is converted into a digital RF signal. The DC offset remover 54 receives the sampled digital RF signal, and removes a DC offset component from the same. A signal output from the DC offset remover 54 is input to the clock recovery circuit 70 and the adaptive digital equalizer 56.
The clock recovery circuit 70 has a frequency and phase error detector 72, a digital loop filter 74, a third D/A converter 76, and a voltage-controlled oscillator 78.
The adaptive digital equalizer 56 uses a FIR filter to equalize, in a desired form, a digital RF signal from which the DC offset component has been removed. Such an equalized digital RF signal is input to the Viterbi decoder 60 and the level error detector 58.
The level error detector 58 calculates an error signal based on a difference between the level of a desired channel and the level of a digital RF signal actually input from the adaptive digital equalizer 56, and applies the calculated error signal to the Viterbi decoder 60 and the adaptive digital equalizer 56. The Viterbi decoder 60 decodes an equalized signal from the adaptive digital equalizer 56 to recover data, and delivers the data to the DP block 90.
The conventional PRML data detection apparatus operates at the maximum speed of 420 MHz, also as a typical operation speed, and uses an FIR filter inside the adaptive digital equalizer 56 to equalize the RF signal. However, such a FIR filter is provided with a series of adders and multipliers, which in itself causes problems, since a resultant chip area cannot be small in size and the operation speed is limited.
Again, the digital loop filter 74 of the clock recovery circuit 70 uses plural adders and multipliers, as in the adaptive digital equalizer 56, which also causes problems, since the chip area is prevented from becoming small in size and the operation speed is very limited.
It has become important to reduce power consumption as battery-operated notebook computers have become widely used, but as noted above the conventional PRML data detection apparatus is prevented from reducing the corresponding power consumption.